1. Field of the Invention
This invention relates to a method for forming a gate electrode employed in a semiconductor device, such as a MOS transistor. More particularly, it relates to a method for forming the gate electrode in which the gate electrode is formed solely by a refractory metal silicide film for satisfying requirements for low cost, low resistance, superior adhesion or high gate voltage withstand characteristics and in which the work function of the gate electrode is controlled for improving the driving capability and accommodation to high degree of size refinement.
2. Description of the Related Art
A complementary MOS transistor (CMOS) circuit, in which an n-type MOS transistor (nMOS) and a p-type MOS transistor (pMOS) are present on one and the same substrate, has such merits that the power consumption is low since the current flows only when both transistors are on, while it lends itself to size refinement or high integration due to its structure and can be operated at a high operating speed. Thus the circuit is extensively used as many LSI constituent elements including memory or logic devices.
The CMOS circuit may be formed not only on a bulk substrate but also on a silicon-on-insulator (SOI) substrate which assures complete device isolation. The use of the SOI substrate having an Si active layer with a thickness on the order of 500 nm leads to suppression of errors in software or to suppression of latch-up, which is a deleterious conduction phenomenon proper to the CMOS circuit, as has been shown since earlier stages of investigations. In addition, it has recently been shown that, if the Si active layer is reduced in thickness to about 100 nm and the channel impurity concentration is lowered to about 1.times.10.sup.17 /cm.sup.3 or less for substantially depleting the Si active layer along its thickness, it becomes possible to achieve desirable performance, such as suppressed low-channel effect or improved current driving capability.
As for gate electrodes of recent MOS transistors, there are two outstanding motifs for researches, namely (i) selection of constituent materials, and (ii) control of the work function for coping with size refinement.
The selection of constituent materials of the motif (i) is explained. As the gate electrode materials for MOS transistors, an n.sup.+ type polysilicon film or a polycide film comprised of the n.sup.+ type polysilicon film layered thereon has hitherto been used. The n.sup.+ polysilicon film is employed since it can withstand a high-temperature process satisfactorily. However, the sheet resistance of the n.sup.+ type polysilicon is as high as approximately 100 ohm/.quadrature. for the film thickness of 100 nm, such that, with progress in LSI size refinement and high integration degree, signal delay due to metallization resistance of the polysilicon gate electrode has been increased to a level which is not negligible in association with the operating speed of LSI. Under such situation, attention has been directed to a refractory metal silicide having a post-annealing resistance about one order smaller than that of the impurity-containing polysilicon layer. Typical of the refractory metal silicide s tungsten silicide (WSi.sub.x). In addition, this material has a work function larger than that of the impurity-containing polysilicon film and is promising for controlling the threshold voltage V.sub.th by the work function. However, the WSi.sub.x film is not employed as a single layer in the gate electrode for the following reason.
First, the WSi.sub.x film is poor in adhesion with respect to an SiO.sub.2 film. If, for example, the WSi.sub.x film is formed by so-called silane reduction CVD, the film is highly susceptible to exfoliation, although irradiation damages to the underlying SiO.sub.2 film may be suppressed satisfactorily in distinction from the case of employing sputtering for deposition in place of CVD. The reason is that F atoms are usually contained in a number on the order of 10.sup.20 /cm.sup.3 in the WSi.sub.x film deposited by silane reduction CVD such that the bonds of Si atoms, which should be bonded to O atoms of the SiO.sub.2 film, are consumed by F-atoms.
The second problem is that the WSi.sub.x film is poor in oxidation and susceptible to crack. With a system such as WSi.sub.x in which W and Si co-exist, there is a probability that Si be oxidized first to form a stable SiO.sub.2 film on its surface. With a system in which Si is supplied in an abundant quantity from outside, the surface of the WSi.sub.x can be protected by this SiO.sub.2 film. However, with the WSi.sub.x alone, the SiO.sub.2 film having a sufficient film thickness to achieve surface protection is not produced, as a result of which volatile WO.sub.x is yielded thus embrittling the produced film.
For the above reason, the WSi.sub.x film is not used alone with the generation since the submicron generation (0.7 to 0.8 .mu.m) but is used extensively used in the from of a so-called W-polycide film (tungsten polycide film) comprised of the WSi.sub.x film layered on the n.sup.+ polysilicon layer as a gate electrode material or a multi-layer metallization material for a memory/logic type device. This is based upon a concept that the polysilicon film which is proven through use and whose characteristics are well-known should be used for an interface with the underlying SiO.sub.2 film and the WSi.sub.x film layered thereon should be responsible for reducing the resistance.
Next, control of the work function associated with size refinement (ii) is explained.
One of the reasons the n.sup.+ type polysilicon film or the polycide film having the refractory metal silicide film layered thereon has hitherto been used as a constituent material for the gate electrode of the MOS transistor is that, since the channel profile is of the buried type, the operating speed may be increased by taking advantage of high bulk mobility, in addition to the fact that heat resistance may be increased as described above. However, since the foremost portions of the depletion layer, protruded form the source/drain region, approach each other in the recessed substrate portion under the effect of the gate electrical field, so that the problem of punch-through tends to be produced. Consequently, with a generation in which the design rules is reduced to lower than a deep submicron range, it becomes difficult with the buried channel type to suppress short channel effects. Therefore, a surface channel type MOS transistor is desired.
It is further demanded of the CMOS that the threshold voltage Vth of nMOS be symmetrical with respect to that of pMOS. With the conventional CMOS circuit employing n.sup.+ type polysilicon film for the gate electrodes of both the nMOS and the pMOS, there is a difference in work function between nMOS and pMOS and, due to such difference, the threshold voltages Vth become non-symmetrical relative to each other. In order for the signal transfer characteristics to be symmetrical relative to each other in case of constituting the basic gate by the CMOS invertor, the Vth values of the two transistors need to be symmetrical relative to each other. Usually, boron is ion-implanted to a shallow depth in the pMOS region for setting the Vth values of the two transistors substantially equal to each other (usually, 1 V or less). However, if the impurity concentration in the vicinity of the substrate surface is increased by ion implantation for Vth adjustment, the carrier mobility in the vicinity of the substrate surface is lowered, which is deleterious to increasing the operating speed.
Similar problems arise with the MOS transistor on the SOI substrate. That is, if attempts are made for setting the value of Vth of the nMOS having the n.sup.+ polysilicon gate electrode to 0.5 to 1.0 V as required for the enhancement type transistor, the required channel impurity concentration is raised to a value exceeding 10.sup.17 /cm.sup.3.
If the device size is refined to a gate length level of 0.1 .mu.m, the absolute number of channel impurity atoms contributing to Vth control per transistor is decreased, such that Vth fluctuations die to statistic variations cannot be relatively neglected, as reported in 1994 Symposium on VLSI technological abstracts, lecture numbers 2.3. In short, there is a certain limit in Vth control employing channel impurity in which the problem of obstructions to high operating speed or fluctuations is inevitably produced. Therefore, if the channel profile is to be of a surface type, and optimum Vth control is to be achieved in the low channel impurity concentration range, it is imperative to control the work function of the gate electrode.
As a specific example of the Vt control by the work function, there is presently known a so-called dual gate type CMOS in which an n.sup.+ type polysilicon film and a p.sup.+ type polysilicon film are used as the gate electrode for the nMOS and the gate electrode for the pMOS, respectively.
In 1994 Symposium on VLSI technological abstracts, lecture number 2.2, there is shown a p.sup.+ -n.sup.+ double gate type MOS transistor. This MOS transistor, employing a p.sup.+ type polysilicon film for a front gate electrode and an n.sup.+ type polysilicon film as a back gate electrode, has succeeded in lowering Vth to less than 0.3 V, while suppressing short channelling effects.
In 1993 IEDM abstracts, lecture number 30.2.1, there is shown a MOS transistor of fully depletion type susceptible to only small Vth fluctuations with temperature in which Vth is lowered to near 0.15 V even although the channel impurity concentration is low.
In 1985 IEDM abstracts, lecture number 15.5, there is shown a CMOS employing a Si-rich MoSi.sub.x gate electrode doped with an impurity on the order of 1+10.sup.12-15. With the CMS, a non-degradable Si layer whose change in Fermi level depends on temperature is segregated in the interface between the MoSi.sub.x film and the gate oxide film for compensating for variation in Vth due to temperature.
However, the W-polycide film, put to practical application under the above-described circumstances, and the Vth control by the work function envisaged up to now, suffer from the following drawbacks.
The problem inherent in the W-polycide film is first discussed.
The W-polycide film is difficult to work anisotropically by dry etching. The reason is that the main etching species of the upper layer side WSi.sub.x is chlorine, while the main etching species for the lower layer side polysilicon film for high selectively etching of polysilicon is bromine, such that the optimum etching conditions differ between the two films, and hence a multi-step process of switching the etching conditions partway becomes necessary if anisotropic etching is to be achieved with the two films. However, with reduction in thickness of the gate electrode, only a small margin is left for switching timing shift, while timing judgment itself becomes difficult with increase in surface steps. Therefore, the W-polycide film is difficult to etch unless the dry etching device exhibits markedly high controllability.
Second, the polysilicon surface needs to be rinsed meticulously before formation of the WSi.sub.x film. During formation of the W-polycide film, the wafer needs to be opened to atmospheric air after forming the polysilicon film. For layering the WSi.sub.x film with good adhesion, it is necessary to remove a native oxide film grown on the polysilicon film surface during the time the polysilicon film is exposed to atmospheric air. The native oxide film is usually removed by dip washing of dipping the wafer in a dilute aqueous solution of hydrofluoric acid. A so-called water mark, a phenomenon in which the native oxide film is left on a wafer portion on which liquid droplets are affixed during wafer drying, is produced, thus seriously lowering the yield. Although it is contemplated to use a cluster tool and to form the polysilicon film and the WSi.sub.x film continuously without exposing the wafer to atmospheric air partway, it is not clear whether or not cost merits could be accrued.
Third, there is a risk of accelerated oxidation of the gate oxide film by layering of the WSi.sub.x film with the polysilicon film. In the WSi.sub.x film, a large quantity of F atoms derived from WF.sub.6 as a gas of the film-forming starting material are captured, as described above. If the F atoms are diffused into the gate oxide film, the reaction shown by the equation EQU SiO.sub.2 +2F.fwdarw.SiF.sub.2 +2O
proceeds to continue capturing F atoms while releasing free oxygen. The oxygen thus released is diffused into a boundary between the gate oxide film and the polysilicon film to allow a new oxide film to grow to induce variations in the thickness of the gate oxides film, as a result of which the threshold voltage Vth of the MOS transistor is fluctuated.
Fourth, the lower layer side polysilicon film does not substantially contribute to reduction in resistance. The overall sheet resistance of the W-polycide film has a limit approximately equal to 20 ohm/.quadrature. for the film thickness of 100 nm (with the WSi.sub.x film thickness of 50 nm and the polysilicon film thickness of 50 nm). Thus the lower layer side polysilicon film is deleterious for achieving size reduction in the height-wise direction.
Fifth, since the W-polycide film has a dual-layer structure, the process is complicated or the number of process steps is inevitably increased in all steps including pre-processing, film formation and film working. This leads to increased production cost for LSI.
Thus the W-polycide film has been used at the cost of the sheet resistance or cost and suffers from peculiar problems inherent in its dual-layer structure. Therefore, if the problems such as adhesion to the SiO.sub.2 film or oxidation could be solved, it is more convenient from resistance and cost considerations to employ the WSi.sub.x film alone as a gate electrode. On the other hand, the WSi.sub.x film, having a work function larger than that of the n.sup.+ type polysilicon film, is effective for Vth control. The same may be said of high-melting metal silicide films other than the WSi.sub.x film.
The problem of conventional Vth control by the work function is discussed.
With the dual gate type CMOS employing n.sup.+ and p.sup.+ type polysilicon films, it is possible to improve punch-through resistance by the nMOS and pMOS channel profile being of the surface channel type. However, it is still necessary to adjust the channel impurity concentration responsive to the work function of the gate electrode. In addition, if the gate length is refined up to the level of 0.1 .mu.m, the channel impurity concentration reaches the order of 10.sup.18 /cm.sup.3, which possibly leads to deterioration of the current driving capability of the transistor.
On the other hand, the technique of employing the p.sup.+-n.sup.+ double gate is limited to the transistor on the SOI substrate. On the other hand, Vth is extremely sensitive to film thicknesses of the Si or gate oxide films as the active regions, thus detracting from device design feasibility.
On the other hand, with the technique of employing the gate electrode with the use of the above-mentioned SiGe, it is difficult to control the work function in the vicinity of the mid band gap.
In addition, with the above-described technique of employing the MoSi.sub.x gate electrode, since the MoSi.sub.x film is formed by sputtering, it is not possible to prohibit increase in the metallization resistance in the step regions caused by poor step coverage or deterioration in voltage withstand characteristics of the gate oxide film caused by ion radiation damage during film formation, so that the technique is insufficient to apply to highly refined future devices.
In short, a variety of the hitherto proposed work function controlling techniques of gate electrodes of the conventional MOS transistors are not completely satisfactory for Vth control.